DSP Algorithm Development for FPGAs and HDL Code Generation

About
Join us for an engaging four-day course that delves into the fundamentals of Digital Signal Processing (DSP) from the perspective of implementation within the FPGA fabric. Particular emphasis will be placed on highlighting the costs, in terms of both resources and performance, associated with implementing various DSP techniques and algorithms. The course will be delivered by world class experts from MathWorks.
Topics include:
- Introduction to FPGA hardware and technology for DSP applications
- DSP fixed-point arithmetic
- Signal flow graph techniques
- Fast Fourier Transform (FFT) Implementation
- Design and implementation of FIR, IIR and CIC filters
- CORDIC algorithm
- HDL code generation for FPGAs
- Integrating handwritten code and existing IP
- Verifying generated HDL code using testbench and cosimulation
OUTLINE
Day 1- DSP for FPGAs
- FPGA Fundamental Concepts
- Signal Flow Graph (SFG) Techniques (SFG) Technique
- Digital Filtering
- Serial Filter Implementation
- Multi-Channel Filter Implementation
Day 2 - DSP for FPGAs
- Frequency Domain Processing
- Multirate Signal Processing for FPGAs
- CORDIC Techniques
- Numerically Controlled Oscillators
- Numerically Controlled Oscillators
Day 3 - Generating HDL Code
- Preparing Models for HDL Code Generation
- Fixed-Point Precision Control
- Generating HDL Code for Multirate Models
- Optimizing Generated HDL Code
Day 4 - Generating HDL Code
- Using Native Floating Point
- Interfacing External HDL Code with Generated HDL
- Verifying HDL Code with Cosimulation
- Hands-on demo
PREREQUISITES
MATLAB® Fundamentals and Signal Processing with Simulink® or equivalent experience.
PRICE
Ticket Type | Early Bird | Standard |
Student - IEEE Member | $1700 | $1800 |
Student - General | $1900 | $2000 |
IEEE Member | $2300 | $2500 |
General | $2800 | $3000 |
SPECIAL OFFERS
To take advantage of our early bird pricing, please register by 31 August 2025 to secure your spot at a discounted rate.
Group discounts are available. Contact the organisers for more details.
Date
Monday 29 September 2025 9:00 AM - Thursday 2 October 2025 5:00 PM (UTC+09:30)Location
University of Adelaide
B16 Ingkarni Wardl, Adelaide SA 5000