DSP algorithm development for FPGAs and HDL code generation
About
This four-day course will review DSP fundamentals from the perspective of implementation within the FPGA fabric. Particular emphasis will be given to highlighting the cost, with respect to both resources and performance, associated with the implementation of various DSP techniques and algorithms.
Topics include:
- Introduction to FPGA hardware and technology for DSP applications
- DSP fixed-point arithmetic
- Signal flow graph techniques
- Fast Fourier Transform (FFT) Implementation
- Design and implementation of FIR, IIR and CIC filters
- CORDIC algorithm
- HDL code generation for FPGAs
- Integrating handwritten code and existing IP
- Verifying generated HDL code using testbench and cosimulation
Prerequisites
MATLAB® Fundamentals and Signal Processing with Simulink® or equivalent experience.
Date
Monday 29 September 2025 9:00 AM - Thursday 2 October 2025 5:00 PM (UTC+09:30)Location
University of Adelaide
B16 Ingkarni Wardl, Adelaide SA 5000
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DSP algorithm development for FPGAs and HDL code generation
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